1. Field of the Invention
The present invention relates to a decoder circuit, and more particularly, it relates to a decoder circuit which is formed by CMOS transistors.
2. Description of the Prior Art
Since the present invention is most applicable to a MOS dynamic RAM formed by CMOS transistors, description is now made with reference to such a MOS dynamic RAM.
With increase in storage capacity of a MOS dynamic RAM, CMOS circuits have been widely employed in view of high-speedness and low power consumption. However, the CMOS circuits have the latch-up problem, whereby N-channel MOS transistor (hereinafter referred to as NMOS transistor) and P-channel MOS transistor (hereinafter referred to as PMOS transistor) cannot be easily provided adjacent to each other for the pattern layout purpose.
In general, a MOS dynamic RAM is necessarily provided with a decoder circuit for selecting a prescribed memory cell from a memory cell array. The following description is made with reference to a 1-of-64 decoder circuit for selecting a single row (or column) from 64 (2.sup.6 =64) rows (or columns) through 6-bit address signals A.sub.0 to A.sub.5.
FIG. 1 is a logic circuit diagram showing an example of a conventional 1-of-64 decoder circuit. Referring to FIG. 1, a 6-input NAND circuit 1.sub.0 is supplied with address signals A.sub.0, A.sub.1, A.sub.2, A.sub.3, A.sub.4 and A.sub.5. An inverter 2.sub.0 is adapted to invert the output from the NAND circuit 1.sub.0, and generates decoded output Y.sub.0. A decoder part 3.sub.0 is thus formed by the NAND circuit 1.sub.0 and the inverter 2.sub.0. Another decoder part 3.sub.1 is similarly formed by a NAND circuit 1.sub.1 and an inverter 2.sub.1. The NAND circuit 1.sub.1 receives address signals A.sub.0 (inverted A.sub.0), A.sub.1, A.sub.2, A.sub.3, A.sub.4 and A.sub.5. Subsequent decoder parts are respectively formed to receive the address signals A.sub.0, A.sub.1, A.sub.2, A.sub.3, A.sub.4 and A.sub.5 and inverted signals A.sub.0, A.sub.1 , A.sub.2, A.sub.3, A.sub.4 and A.sub.5 thereof orderly in different combinations in the 6-input NAND circuits. The last decoder part 3.sub.63 is formed by a 6-input NAND circuit 1.sub.63 supplied with the address signals A.sub.0, A.sub.1, A.sub.2, A.sub.3, A.sub.4 and A.sub.5 and an inverter 2.sub.63.
In the circuit as shown in FIG. 1, the output Y.sub.0 goes high only when all of the address signals inputted in the 6-input NAND circuit 1.sub.0 are at "H" levels, to be in a selected state. When, to the contrary, at least one of the address signals inputted in the 6-input NAND circuit 1.sub.0 is at an "L" level, the output Y.sub.0 goes low to be in an unselected state. Therefore, with respect to 2.sup.6 =64 combinations of the address signals A.sub.0 to A.sub.5, only one of the decoder parts can be selected while keeping the remaining 63 decoder parts in unselected states. This is the basic operation of the decoder circuit.
FIG. 2 is a circuit diagram showing the decoder part 3.sub.0 as shown in FIG. 1, which is simply formed by a CMOS circuit. The 6-input NAND circuit 1.sub.0 is formed by six PMOS transistors connected in the parallel form and six NMOS transistors connected in the series form. The inverter 2.sub.0 is formed by a PMOS transistor serving as a loading transistor and an NMOS transistor serving as a driver transistor. These transistors are formed by well-known methods, and hence detailed description thereof is omitted.
The pitch of a decoder circuit employed for a MOS dynamic RAM is determined by that of word lines forming the memory cell array. Such pitch of the word lines has been reduced with increase in the storage capacity of the MOS dynamic RAM. In case of a 1-Mbit MOS dynamic RAM, for example, the pitch of word lines is about 4 .mu.m. When the 1-of-64 decoder circuit as shown in FIG. 1 is formed by the CMOS circuits as shown in FIG. 2, the respective decoder parts 3.sub.0 to 3.sub.63 as shown in FIG. 1 must be subjected to pattern layout in the pitch of 4 .mu.m. Consequently, the NMOS transistors and the PMOS transistors forming the 6-input NAND circuits 1.sub.0 to 1.sub.63 must be subjected to pattern layout in an adjacent manner, and such adjacent pattern layout easily causes a latch-up phenomenon. Thus, it is extremely important to enlarge the pitch between adjacent decoder parts, in order to prevent the latch-up phenomenon.
FIG. 3 illustrates another example of a conventional 1-of-64 decoder circuit employed for enlarging the pitch of the decoder circuit formed by CMOS circuits. Referring to FIG. 3, each decoder part is formed by a main decoder part A and four subdecoder parts B.sub.0 to B.sub.3. The main decoder part A is formed by a 4-input NAND circuit 4, which receives address signals A.sub.0, A.sub.1, A.sub.2 and A.sub.3. The subdecoder part B.sub.0 is formed by a PMOS transistor T.sub.0 and an NMOS transistor T.sub.0 '. The PMOS transistor T.sub.0 has a drain supplied with a predecoded signal P.sub.0, a source connected with an output end deriving output Y.sub.0 and a gate connected to an output node N1 of the 4-input NAND circuit 4. The NMOS transistor T.sub.0 ' has a drain connected to the output end deriving the output Y.sub.0, a grounded source and a gate connected to the node N1. In a similar manner of connection, the subdecoder part B.sub.1 is formed in correspondence to a predecoded signal P.sub.1 and the subdecoder part B.sub.2 is formed in correspondence to a predecoded signal P.sub.2, while the subdecoder part B.sub.3 is formed in correspondence to a predecoded signal P.sub.3. 16 such decoder parts as shown in FIG. 3 are provided to obtain 64 decoded outputs Y.sub.0 to Y.sub.63. The main decoder parts A of the 16 decoder parts are supplied with address signals in different combinations.
FIG. 4 shows a circuit for generating the four predecoded signals P.sub.0 to P.sub.3 used in the decoder circuit as shown in FIG. 3. As obvious from FIG. 4, this circuit is adapted to generate the predecoded signals P.sub.0 to P.sub.3 by decoding address signals A.sub.4, A.sub.4, A.sub.5 and A.sub.5 through 2-input NAND circuits 5.sub.0 to 5.sub.3 and inverters 6.sub.0 to 6.sub.3.
The decoder circuit as shown in FIG. 3 can perform pattern layout of the main decoder parts A in the pitch four times longer than that of the decoder circuit as shown in FIG. 1. With respect to the subdecoder parts, no pattern layout problem is caused since the transistors employed therefor are small in size and can be arranged in deviation along the horizontal direction of FIG. 3. In the circuit as shown in FIG. 3, therefore, the degree of adjacency of the NMOS transistors and the PMOS transistors can be relaxed. However, when the circuit as shown in FIG. 3 is applied to a 1-Mbit MOS dynamic RAM, each decoder part must be subjected to pattern layout in the pitch of 16 .mu.m (4 .mu.m.times.4), which value is not sufficient in view of the latch-up problem. Further, the decoder circuit as shown in FIG. 3 cannot cope with a mass storage memory having storage capacity exceeding 4 Mbits.
FIG. 5 shows still another example of a conventional decoder circuit proposed for enlarging the pitch of the decoder circuit. The circuit as shown in FIG. 5 is formed on the basis of the decoder circuit as shown in FIG. 3, to increase the number of predecoded signals from 4 to 16. Therefore, this circuit is substantially identical in basic operation to the circuit as shown in FIG. 3.
FIG. 6 shows a circuit for generating predecoded signals P.sub.0 to P.sub.15 used in the decoder circuit as shown in FIG. 5. The circuit as shown in FIG. 6 is adapted to generate the predecoded signals P.sub.0 to P.sub.15 by decoding address signals A.sub.2, A.sub.2, A.sub.3, A.sub.3, A.sub.4, A.sub.4, A.sub.5 and A.sub.5 by 4-input NAND circuits 8.sub.0 to 8.sub.15 and inverters 9.sub.0 to 9.sub.15.
The decoder circuit as shown in FIG. 5 can perform pattern layout of main decoder parts A in the pitch 16 times longer than that of the decoder circuit as shown in FIG. 1. When this circuit is applied to a 1-Mbit MOS dynamic RAM, therefore, the pitch thereof is 64 .mu.m (4 .mu.m.times.16), which value is sufficiently allowable in view of the latch-up problem. However, increase in the area for wiring 16 predecoded signals and that of the circuit for generating the 16 predecoded signals are not negligible in view of pattern layout. Further, increase in stray capacitance by the gate capacitance of 16 NMOS transistors T.sub.0, T.sub.1, . . . , T.sub.15 and 16 PMOS transistors T.sub.0 ', T.sub.1 ', . . . , T.sub.15 ' connected to an output node N1 of each main decoder part A hinders high-speed operation of the decoder circuit.
In the conventional decoder circuit as hereinabove described, enlargement of the pattern layout pitch for each decoder part leads to increase in number of predecoded signals with increase in the circuit area, while the operating speed of the circuit cannot be increased by increase in stray capacitance.